The present invention relates to a semiconductor apparatus having an array of memory cells each comprising complex oxides for forming an insulation film of an information storing capacitor thereof and a manufacturing method therefor, and more particularly to structures of a wiring portion for connecting a cell transistor and a cell capacitor, a contact portion of a bit line and a memory cell in a ferroelectric random access memory (FRAM) having a ferroelectric insulation film for a capacitor and a method of forming the same, and to a structure of a memory cell of a dynamic random access memory (DRAM) having an array of dynamic memory cells having a capacitor insulation film made of dielectric material and a method of forming the same.
In recent years, a non-volatile ferroelectric memory cell (a FRAM cell) and a FRAM having the foregoing memory cell array comprising, as an interelectrode insulation film of a capacitor for storing information, a ferroelectric thin film made of a material having a perovskite structure or a layered perovskite structure have attracted attention.
The ferroelectric film has a characteristic such that electric polarization generated once when an electric field has been applied is retained even if the electric field is removed and the direction of the polarization is inverted when an electric field having intensity exceeding a certain level is applied into a direction opposite to the direction of the foregoing electric field.
Taking notice of the characteristic of the dielectric material for inverting the direction of polarization, a technique has been developed to realize a FRAM cell by employing a ferroelectric material to form an insulation film of an information storing capacitor of a memory cell.
The FRAM cell has a structure in which a ferroelectric capacitor is substituted for a capacitor of a DRAM cell. The FRAM employs a method (a data destructive reading method) in which a charge in a polarization switched or non-switched state is fetched from a ferroelectric capacitor through a switching MOS transistor. Thus, the FRAM has a characteristic that data written and stored on a memory cell is not lost even if the operating power source is turned off.
The FRAM, which is the non-volatile memory, has a characteristic such that the FRAM does not require a refreshing operation to store data and no electric power is-required in a standby mode, as compared with the DRAM which is a representative large-capacity memory. When the FRAM is compared with a flash memory, which is another non-volatile memory, the FRAM has a characteristic that a great number of data rewriting times is permitted and data can significantly quickly be rewritten. When the FRAM is compared with a SRAM (Static Random Access Memory) which is used in a memory card or the like and which is needed to be backed up by a battery, the FRAM has characteristics that the electric power consumption can be reduced and the area of the cell can significantly be reduced.
The FRAM having the above-mentioned characteristics are significantly expected to be substituted for the conventional DRAM, the flash memory and the SRAM and applied to a logic circuit consolidation device and the like. Since the FRAM is able to operate at high speed without any battery, development to a non-contact ID card (RF-ID: Radio Frequency-Identification Data) has been commenced.
The structure of the memory cell in the FRAM is classified into two main types. One of the structures is arranged such that a ferroelectric film is, in place of a para-electric film, used to form a storage capacity which is as well as employed in the DRAM and which is arranged to store a charge capacity serving as information. Another structure is arranged such that a ferroelectric film is, in place of a silicon oxide film, employed to form a gate insulation film of the MOSFET. The latter structure, having no appropriate ferroelectric film which can directly be formed on a silicon layer, cannot practically be used. Since the latter structure has simply been suggested until today, the FRAM is usually the former structure.
The FRAM cell includes a 1-transistor/1-capacitor (abbreviated to 1T/1C) structure composed of one transistor Q and one ferroelectric capacitor C as shown in FIG. 1 and a 2-transistor/2-capacitor (abbreviated to 2T/2C) structure composed of two transistors Q1 and Q2 and two ferroelectric capacitors C1 and C2, for example, as shown in FIG. 3A.
Although the 1T/1C structure has an advantage in that a dense integration similarly to the DRAM is permitted, variation of the ferroelectric characteristics of the memory cells and variation of deterioration must be prevented in order to realize memory cells capable of preventing variation of their characteristics. Thus, the foregoing structure has a problem in that the manufacturing yield and the reliability as the device cannot easily be improved.
Although the 2T/2C structure has a problem in that an area which is two times the area required for the 1T/1C is required, a great characteristic margin is permitted and thus the manufacturing yield and the reliability as the device can be improved.
Both of the foregoing structures are formed such that a stacked structure of an electrode/ferroelectric member/electrode is formed on the base insulation film, Al or Cu wiring is performed through a contact hole formed in the oxide film on the stacked structure, and a passivation film is formed to serve as a protective film.
Since the FRAM cell is able to operate at high speed with small electric power consumption and a highly integrated structure is expected as described above, the reduction of the area for the memory cells and a manufacturing process which does not considerably deteriorate the ferroelectric member must be realized. Moreover, a multilayer wiring technique has not been established which is required when the conventional FRAM is consolidated with another device or when a highly integrated structure is formed.
The reason why the semiconductor integrated circuit having the FRAM device mounted thereon cannot easily be formed into a multilayered wiring structure is that the ferroelectric material has a low tolerance to a reducing atmosphere (in particular, a hydrogen atmosphere). Since the conventional LSI processes almost include a process in which hydrogen is mixed, a critical problem arises when the FRAM is manufactured.
As an example of the process in which hydrogen is mixed, a process for plugging a via hole in a multilayered wiring structure is exemplified. As a method of embedding a via hole having a large aspect ratio, a process for embedding tungsten by a CVD method is usually employed. Since the process for embedding tungsten encounters generation of a multiplicity of hydrogen groups, the ferroelectric is damaged critically.
The foregoing problem will specifically be described.
Hitherto, the ferroelectric memory cell has been formed by (1) a structure in which a bit line is formed later such that a ferroelectric capacitor is formed below the bit line; and (2) a structure in which the bit line is formed previously such that the bit line is formed below the ferroelectric capacitor.
When the ferroelectric memory cell is manufactured which has the structure in which the bit line is formed later, the ferroelectric capacitor is formed on a switching MOS transistor. Then, a lower electrode of the ferroelectric capacitor and the MOS transistor are connected to each other by a polysilicon plug, and then the bit line is formed on the ferroelectric capacitor.
When the ferroelectric capacitor is formed, the lower electrode of the ferroelectric capacitor is formed by, usually, using Pt (platinum) on the polysilicon plug, followed by forming the ferroelectric thin film. When the ferroelectric thin film is crystallized, oxidation annealing at high temperatures must be performed.
When PZT (lead-zirconate-titanate) is employed as the ferroelectric material, a defect caused from diffusion of Pb in the PZT occurring due to insufficient oxidation results in deterioration of the characteristics of the capacitor. To prevent this, sufficient oxidation must be performed in which oxidation annealing must be performed usually at 600.degree. C. to 700.degree. C.
When a bismuth layered compound, such as SBT (strontium-bismuth-tantalate), is employed as the ferroelectric material, the oxidation annealing must be performed at high temperatures of about 800.degree. C.
However, the foregoing high temperature oxidation annealing encounters a problem in that the lower electrode including Pt reacts with the polysilicon plug and thus formed into silicide or the polysilicon plug is unintentionally oxidized.
When the ferroelectric memory cell having the structure in which the bit line is formed previously is manufactured, the bit line is formed on the switching transistor. Then, the ferroelectric capacitor is formed on the bit line. When the lower electrode (including, for example, Pt) of the ferroelectric capacitor and the switching transistor are, in this case, connected to each other by a polysilicon plug, there arises a problem similar to that experienced with the structure in which the bit line is formed later.
Accordingly, an upper electrode connection structure has been suggested in which an upper electrode of the ferroelectric capacitor and the switching transistor are directly connected to each other by a local electric line in the form of an embedded electric line. The foregoing structure has an advantage that the pattern layout of the ferroelectric capacitor can relatively freely be determined. When the ferroelectric capacitor is disposed on both the switching transistor region and the device isolation region, a precise structure can be realized.
The above-mentioned structure in which the bit line is formed previously and the upper electrode is connected is formed by the steps of forming the portion from the lower electrode (a plate electrode) of the ferroelectric capacitor to the upper electrode, and depositing a film for protecting the capacitor. Then, the local wiring for directly connecting the upper electrode and the switching transistor to each other is formed by opening, in the film for protecting the capacitor, a contact portion with the upper electrode and a contact portion with an active layer of the transistor. Then, the wiring film is deposited in the opening portions, followed by performing a patterning operation.
In the structure in which the bit line is formed previously and the upper electrode is connected, the operation for connecting the lower electrode (including, for example, Pt) of the ferroelectric capacitor and the switching transistor to each other by the polysilicon plug does not raise the above-mentioned problem in that the lower electrode reacts with the polysilicon plug and the same is formed into silicide. However, the aspect ratio and step coverage which are required to form a precise structure result in that the local wiring for directly connecting the upper electrode and the transistor to each other cannot easily be formed.
When the PZT or BST (barium-strontium-titanate) is employed as the ferroelectric material, the reducing atmosphere included in the CVD (Chemical Vapor Deposition) process for forming the wiring after the ferroelectric thin film has been formed raises a problem. In this case, there arises a problem in that the characteristics of the ferroelectric material deteriorate owning to the reduction reaction.
That is, when the local wiring for connecting the upper electrode and the switching transistor to each other is formed such that tungsten plug is embedded by forming a tungsten film in an intense reducing atmosphere (hydrogen type gas) in a metal CVD apparatus which has been employed to manufacture the DRAM, the characteristics (electric characteristics, such as remanant polarization) of the ferroelectric capacitor deteriorate.
Also in a case where the local wiring for connecting the upper electrode and the switching transistor to each other is formed such that a MO (Metallo-Organic) CVD is employed to form an aluminum wiring film, the characteristics of the ferroelectric capacitor deteriorate. The reason for this is that the hydrogen group components including the source materials cannot completely be removed and thus the reducing atmosphere retains.
When PZT or BST is employed as the ferroelectric material, noble metal, such as Pt, Ir, an Ir oxide (IrO.sub.2), Ru, a Ru oxide (RuO.sub.2), a LSCO (lanthanum-strontium-cobalt or copper-oxide) or SRO (strontium-ruthenium-oxide) or other conductive oxides can be employed.
However, the foregoing materials cannot easily precisely be processed to sub-micron level of about 0.5 .mu.m by RIE (reactive ion etching), ion milling or ECR etching (electron cyclotron resonance etching). In particular, Pt cannot easily precisely be processed to be used to form a precise ferroelectric capacitor. However, the ferroelectric memory cell must precisely be formed to design a highly integrated ferroelectric Memory. To form a precise memory cell, it is an important fact to precisely form the upper electrode of the ferroelectric capacitor.
On the other hand, the degree of integration of the semiconductor memory has been raised year after year. Although the size has been reduced, the electric capacity of the dielectric capacitor for storing charges must be not smaller than about 30 fF. To achieve this, the effective area of the capacitor must be enlarged, the thickness of the dielectric film must be reduced or the dielectric constant of dielectric material must be raised. The conventional technique for DRAM has been attempted to stereoscopically form the capacitor and reduce the thickness of the same by mainly improving the two former factors. However, the stereoscopically forming the capacitor by the conventional SiO.sub.2 type dielectric film and reducing the thickness of the film have limitations. Therefore, a technique for depositing a thin film of a dielectric material having a high dielectric constant has been required.
When a capacitor having the stacked structure of the electrode/the ferroelectric material/the electrode which is employed in the FRAM or the that having the stacked structure of the electrode/the dielectric material having a higher dielectric constant/the electrode which is employed in the DRAM is manufactured, the noble metal, such as Pt, Ir, Ru, IrO.sub.2, RuO.sub.2, LSCO or SRO or the conductive oxides are, as described above, employed as the material of the electrode.
As the ferroelectric material for the FRAM cell capacitor, an oxide including perovskite structure, such as PZT (Pb (Zr, Ti) O.sub.3), SBT (SrBi.sub.2 (Ta, Nb).sub.2) or BIT (Bi.sub.4 Ti.sub.3 O.sub.12) or an oxide in the form in which a substitutional element is substituted for a portion of each of the foregoing oxides is employed. As the dielectric material of the DRAM cell capacitor, BST ((Ba, Sr) TiO.sub.3) or the like is employed.
As a method of forming the ferroelectric film or the dielectric film, a spin coating method, such as sputtering, laser ablation, CVD, MOD (Metallo-Organic Decomposition) or sol-gel method or a LSMCD (Liquid Source Misted Chemical Deposition) method in which a mist MOD material is guided to an upper surface of a wafer by a carrier gas to deposit the material while using ultraviolet rays for assistance are known.
The sputtering method is a film forming method with which mass production can satisfactorily be performed. Since two electrodes (made of metal or a conductive oxide) on both sides of the dielectric material can be formed by the same sputtering method, the throughput can easily be improved.
Since the sputtering method and the laser ablation method are methods each having the step of forming the film in an atmospheric gas of N.sub.2, Ar, Ar/O.sub.2 or the like, unintentional introduction of the components of the gas into the film cannot be prevented during the film forming process. Thus, voids are, due to the retained gas, formed in a complex oxide film (an oxide film containing at least two or more types of metal elements). As a result, there arises a problem in that a dense oxide film cannot be formed.
In actual, a sputter gas of Ar or the like is detected from the film immediate after the deposition process. The above-mentioned methods have the step of guiding gas molecules near the target with large energy of plasma so as to be made incident upon the film. Since the foregoing mechanism is different from diffusion or the like, large energy is retained and residual gas can easily be implanted into the film as the sputtering pressure is low. Since the film immediate after the deposition is an amorphous film or a crystal film having a low density, the residual gas can be dispersed and thus the gas is inconspicuous. However, if the film is subjected to a heat treatment for crystallization, the residual gas is left in the grain boundary and/or the interface of the crystal and thus apparent voids are formed.
If the heat treatment is performed in a short time, large voids are formed in the grains as well as in the grain boundary and the interface. Since also the film forming process, such as the CVD or the LSMCD, uses a carrier gas for introducing the raw material into the chamber, the carrier gas is introduced into the film. Thus, voids are formed in the comp lex oxide film attributable to the residual gas, similarly to the sputtering process.
The size of the void is determined when the annealing process is performed after the film forming process to crystallize the film or to raise the density. If the annealing operation is a rapid thermal processing in which the rate at which the temperature is raised is high, apparent voids are formed. That is, the crystallizing annealing operation of the complex oxide film, required to perform the rapid thermal processing in order to minimize diffusion and evaporation, encounters a problem in that a dense film cannot be formed because of the above-mentioned problems.
However, a ferroelectric film having a low film density suffers from reduction of the polarization quantity and thus a satisfactory operating margin cannot be realized. Moreover, it cannot be operated with low voltages. What is worse, short circuit easily occurs when a thin film is formed. There arises another problem in that the characteristics are excessively changed attributable to the atmosphere in the post process. If voids are formed in also the electrode film because of the same reasons and thus the density of the film is lowered, the resistance of the film is raised and thus a problem arises in that the operation speed is lowered.
As described above, the conventional ferroelectric memory cannot easily prevent deterioration of the characteristics of the ferroelectric capacitor and integrate the manufacturing process.